#define     AXI_DMAC_BASE               0x86000000      //X1_APB SLAVE0

//common reg's address define
#define     DMAC_CFGREG                 AXI_DMAC_BASE+0x10
            //b1   :   INT_EN   //Global interrupt Enable bit
            //b0   :   DMAC_EN  //DW_axi_dmac Enable bit

#define     DMAC_CHENREG                AXI_DMAC_BASE+0x18
            //[b7:b0]  :  Channel[x] //Channel x Enable bit
            //[b15:b8] :  Enable write to Channel[x] En bit
            //[b23:b16]:  Suspend request bit for Channel[x]
            //[b31:b24]:  Enable write to Channel[x] Suspend req bit
            //[b39:b32]:  Abort request of Channel[x] 
            //[b47:b40]:  Enable write to Channel[x] Abort req bit

//#define     DMAC_CHENREG2               AXI_DMAC_BASE+0x18

#define     DMAC_INTSTATUSREG           AXI_DMAC_BASE+0x30
            //[b7:b0]  :  RO,Channel[x] Interrupt Status Bit
            //[16]     :  RO,Common reg Interrupt Status Bit

#define     DMAC_COMMONREG_INTCLEARREG  AXI_DMAC_BASE+0x38
            //

#define     DMAC_COMMONREG_INTSTATUS_ENABLEREG AXI_DMAC_BASE+0x40  //slave access error

#define     DMAC_COMMONREG_INTSIGNAL_ENABLEREG AXI_DMAC_BASE+0x48  //slave access error

#define     DMAC_COMMONREG_INTSTATUSREG AXI_DMAC_BASE+0x50  //slave access error
            //b0  :  Slave if Common Reg Decode Error Status Bit
            //b1  :  Slave if Common Reg Write to RO Error
            //b2  :  Read to WO Error
            //b3  :  Write On Hold error
            //b6:b4:  RSVD
            //b7  :  Write Parity Error
            //b8  :  Undefined register Decode Error
            //b20:b9:ECC Error from axi_bus

#define     DMAC_RESETREG               AXI_DMAC_BASE+0x58
            //b0  :  Write 1 to reset dmac, sw is not allowed to write this bit to 0


//CH[x] REGS, (x=1; x<=DMAX_NUM_CHANNELS)
//------------------------------------------------------------------------
//Channel 1
#define     CH1_SAR                     AXI_DMAC_BASE+0x100+0*0x100
            //b63:b0 :  Current Source Address of DMA Transfer

#define     CH1_DAR                     AXI_DMAC_BASE+0x108+0*0x100
            //b63:b0 :  Current Destination Address of DMA Transfer

#define     CH1_BLOCK_TS                AXI_DMAC_BASE+0x110+0*0x100
            //b63:22 :  RSVD
            //b21:b0 :  Block Transfer SIZE  (BLOCK_SIZE+1)

#define     CH1_CTL                     AXI_DMAC_BASE+0x118+0*0x100
            //b0     :  SMS, Source master Select 0/1
            //b1     :  RSVD
            //b2     :  DMS, Destination Master Select 0/1
            //b3     :  RSVD
            //b4     :  SINC, Source Address Increment 0:INC 1:FIXED
            //b5     :  RSVD
            //b6     :  DINC, Destination Address Increment 0:INC 1:FIXED
            //b7     :  RSVD
            //b10:b8 :  SRC_TR_WIDTH, Source Transfer Width 000~110: 8bit~512bit (arsize) 
            //b13:b11:  DST_TR_WIDTH, Source Transfer Width 000~110: 8bit~512bit (awsize)
            //b17:b14:  Source Burst Transaction Lenth, <= DMAX_CHx_MAX_MSIZE
            //b21:b18:  Destination Burst Transaction Lenth,not related to awlen signal
            //b25:b22:  AR_CACHE, map to ar_cache signal
            //b29:b26:  AW_CACHE, map to aw_cache signal
            //b30    :  Non Posted Last Write Enable
            //b31    :  RSVD
            //b34:b32:  AR_PROT, map to ar_prot signal
            //b37:b35:  AW_PROT, map to aw_prot signal
            //b38    :  ARLEN_EN, Source Burst Lenth Enable, define AR_LEN domain is en/dis
            //b46:b39:  ARLEN, Source Burst Lenth, <= DMAX_CHx_MAX_AMBA_BURST_LENTH
            //b47    :  AWLEN_EN, Destination Burst Lenth Enable, define AW_LEN domain is en/dis
            //b55:b48:  AWLEN, Desination Burst Lenth, <= DMAX_CHx_MAX_AMBA_BURST_LENTH
            //b56    :  SRC_STAT_EN, Source Status Enable
            //b57    :  DST_STAT_EN, Destination Status Enable
            //b58    :  Interrupt On completion of Block Transfer
            //61:59  :  RSVD
            //62     :  Last Shadow Register/Linked List Item
            //63     :  Shadow Register content/linked list Item valid

#define     CH1_CFG2                    AXI_DMAC_BASE+0x120+0*0x100
            //b1:b0  :  Source Multi Block Transfer type : 00/01/10/11
            //b3:b2  :  Destination Multi Block Transfer type
            //b8:b4  :  Assign hs if to the source of channel[x]
            //b10:b9 :  RSVD
            //b15:b11:  Assign hs if to the destination of channel[x]
            //b17:b16:  RSVD
            //b21:b18:  Number of AXI Unique ID's for AXI READ-CH
            //b24:b22:  RSVD
            //b28:b25:  Number of AXI Unique ID's for AXI WRITE-CH
            //b31:b29:  RSVD
            //b34:b32:  TT_FC,Transfer Type and Flow Control :
                        //0x0: m2m,dmac    0x1:m2p,dmac
                        //0x2: p2m,dmac    0x3:p2p,dmac
                        //0x4: p2m,srcp    0x5:p2p,srcp
                        //0x6: m2p,dstp    0x5:p2p,dstp
            //b35    :  Source sw/hw hand-shaking select    0:hw  1:sw
            //b36    :  Destination sw/hw hand-shaking select    0:hw  1:sw
            //b37    :  Source hw hand-shaking polarity   0:active high  1:active low
            //b38    :  Destination hw hand-shaking polarity   0:active high  1:active low
            //b46:b39:  RSVD
            //b51:b47:  CH_PRIOR, channel priority
            //b52    :  LOCK_CH, channel lock bit
            //b54:b53:  LOCK_LEVEL, 00:Over complete /01:Over block
            //b58:b55:  Source Outstanding Request limit , <= 16  (LIMIT=Value+1)
            //b62:b59:  Destination Outstanding Request limit , <= 16  (LIMIT=Value+1)
            //b63    :  RSVD

#define     CH1_STATUSREG               AXI_DMAC_BASE+0x130+0*0x100
            //b21:b0 :  Completed transfer size
            //b31:b22:  RSVD
            //b46:b32:  Data left in CH-FIFO after completing current block transfer 
            //b63:b47:  RSVD

#define     CH1_SWHSSRCREG              AXI_DMAC_BASE+0x138+0*0x100
            //b0     :  Sw hs req for channel source
            //b1     :  Write enable for b0
            //b2     :  Sw hs single req for channel source (burst_lenth=1)
            //b3     :  Write enable for b2
            //b4     :  Sw hs last request for channel source
            //b5     :  Write enable for b4
            //b63:b6 :  RSVD

#define     CH1_SWHSDSTREG              AXI_DMAC_BASE+0x140+0*0x100

#define     CH1_AXI_IDREG               AXI_DMAC_BASE+0x150+0*0x100
            //b2:b0  :  AXI Read ID Suffix
            //b18:b16:  AXI WRITE ID Suffix

#define     CH1_SSTAT                   AXI_DMAC_BASE+0x160+0*0x100
            //b31:b0 :  Source Status

#define     CH1_DSTAT                   AXI_DMAC_BASE+0x168+0*0x100

#define     CH1_SSTATAR                 AXI_DMAC_BASE+0x170+0*0x100

#define     CH1_DSTATAR                 AXI_DMAC_BASE+0x178+0*0x100

#define     CH1_INTSTATUS_ENABLEREG     AXI_DMAC_BASE+0x180+0*0x100
#define     CH1_INTSTATUS               AXI_DMAC_BASE+0x188+0*0x100
#define     CH1_INTSIGNAL_ENABLEREG     AXI_DMAC_BASE+0x190+0*0x100
#define     CH1_INTCLEARREG             AXI_DMAC_BASE+0x198+0*0x100


